APA (7th ed.) Citation

Parameshwara, M. C., Maroof, N., & Khan, A. (2022). Majority logic based area-delay efficient 1-bit approximate adder for error-tolerant applications. Engineering Research Express, 4(2), 25033-25043. https://doi.org/10.1088/2631-8695/ac7282

Chicago Style (17th ed.) Citation

Parameshwara, M C., Naeem Maroof, and Angshuman Khan. "Majority Logic Based Area-delay Efficient 1-bit Approximate Adder for Error-tolerant Applications." Engineering Research Express 4, no. 2 (2022): 25033-25043. https://doi.org/10.1088/2631-8695/ac7282.

MLA (9th ed.) Citation

Parameshwara, M C., et al. "Majority Logic Based Area-delay Efficient 1-bit Approximate Adder for Error-tolerant Applications." Engineering Research Express, vol. 4, no. 2, 2022, pp. 25033-25043, https://doi.org/10.1088/2631-8695/ac7282.