Majority logic based area-delay efficient 1-bit approximate adder for error-tolerant applications

• Published in: Engineering Research Express Vol. 4; no. 2; pp. 25033 - 25043
• Main Authors: Parameshwara, M C, Maroof, Naeem, Khan, Angshuman
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.06.2022
• Subjects: approximate adder; error-tolerant; inexact adder; majority gate adder; quantum-cellular- automata
• ISSN: 2631-8695; 2631-8695
• DOI: 10.1088/2631-8695/ac7282

The complementary metal oxide semiconductor (CMOS) technology is approaching its physical limits due to lithographic issues and diminishing benefits of scaling. The new technologies such as quantum dot cellular automata (QCA), tunneling phase logic (TPL), nonmagnetic logic (NML), single electron tunneling (SET), etc are emerging as an alternative and may supersede the conventional CMOS technologies in the near future. Now days, the design of approximate computing based on QCA technologies has gaining much of recent interest. In this paper, a majority-logic (ML) based area-delay efficient novel approximate full adder (AFA) is presented. The QCA layout of proposed AFA is designed and simulated using QCADesigner tool. Further, the proposed AFA is analyzed and compared against the state-of-the-art approximate adders referred to as ‘reported AFAs’ (RAAs), in terms of error metrics (EMs), area, and time complexity. Also, analyzed its efficacy for error-tolerant applications such as image processing.