Address Translation Aware Memory Consistency

Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need.

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Bibliographic Details
Published inIEEE MICRO Vol. 31; no. 1; pp. 109 - 118
Main Authors Romanescu, B, Lebeck, A, Sorin, D J
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.01.2011
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Adaptation model
address translation
Coherence
Computer memory
Computer programming
Computer science
Computer simulation
Computer systems
Consistency
Design engineering
dynamic verification
Faults
Instruction sets
Load modeling
Mathematical models
Memory
Memory consistency
Specifications
Synchronization
Systems analysis
Translation systems
Translations
virtual memory
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Summary:Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2010.99