Address Translation Aware Memory Consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need.
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Published in | IEEE MICRO Vol. 31; no. 1; pp. 109 - 118 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
Los Alamitos
IEEE
01.01.2011
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0272-1732 1937-4143 |
DOI: | 10.1109/MM.2010.99 |