The SARC Architecture

The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfer...

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Bibliographic Details
Published inIEEE MICRO Vol. 30; no. 5; pp. 16 - 29
Main Authors Ramirez, A, Cabarcas, F, Juurlink, B, Alvarez Mesa, Mauricio, Sanchez, F, Azevedo, A, Meenderinck, C, Ciobanu, C, Isaza, S, Gaydadjiev, G
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.09.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
accelerator
Accelerator boards
Accelerators
Architecture
Computer architecture
Computer memory
Data transfer (computers)
Decoding
Engines
heterogeneous architecture
Microprocessors
multicore
Multicore processing
Parallel processing
Programming
programming model
Runtime
Schedules
System-on-a-chip
Tasks
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Summary:The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2010.79