Background Digital Calibration of Comparator Offsets in Pipeline ADCs

This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus rel...

Full description

Saved in:
Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 7; pp. 1345 - 1349
Main Authors Gines, Antonio Jose, Peralias, Eduardo, Rueda, Adoracion
Format Journal Article
LanguageEnglish
Published IEEE 01.07.2015
Subjects
Accuracy
Background calibration
Calibration
comparator offset
digital blind estimation
Estimation
flash and pipeline ADCs
Indexes
Pipelines
Redundancy
Topology
Background calibration
comparator offset
digital blind estimation
flash and pipeline ADCs
Online AccessGet full text

Cover

More Information
Summary:This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2014.2335233