A 1.03MOPS/W Lattice-based Post-quantum Cryptography Processor for IoT Devices

This work introduces a configurable lattice-based post-quantum cryptography processor designed specifically for lightweight IoT devices. It accelerates the computation of Key-Encapsulation Mechanism (KEM) and Digital Signature Algorithm (DSA) based on module learning with errors algorithm (MLWE). In...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 24; no. 1; pp. 55 - 61
Main Authors Kim, ByungJun, Mun, Han-Gyeol, Kim, Shinwoong, Lee, JongMin, Sim, Jae-yoon
Format Journal Article
LanguageEnglish
Published 대한전자공학회 01.02.2024
Subjects
전기공학
Post-quantum cryptography
accelerator
security
learning-with errors
lattice-based cryptography
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Summary:This work introduces a configurable lattice-based post-quantum cryptography processor designed specifically for lightweight IoT devices. It accelerates the computation of Key-Encapsulation Mechanism (KEM) and Digital Signature Algorithm (DSA) based on module learning with errors algorithm (MLWE). In order to minimize both hardware cost and energy consumption, the processor incorporates a Barrett reduction algorithm method for efficient number-theoretic transform calculations and implements real-time processing for polynomial sampling. The chip is fabricated on a 28 nm CMOS technology process. It achieves the state-of-the-art power efficiencies and latency in MLWE-based PQC. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
2233-4866
1598-1657
DOI:10.5573/JSTS.2024.24.1.55