Vertical channel nMOSFET with an asymmetric graded lightly doped drain

A novel vertical channel nMOSFET with an asymmetric graded lightly doped drain (AGLDD) is first proposed and experimentally demonstrated. The vertical AGLDD structure is achieved by conventional ion implantation and impurity diffusion. The device fabrication is compatible with planar CMOS technology...

Full description

Saved in:
Bibliographic Details
Published inMicroelectronic engineering Vol. 77; no. 3; pp. 365 - 368
Main Authors Zhou, F.L., Huang, R., Zhang, X.
Format Journal Article
LanguageEnglish
Published Amsterdam Elsevier B.V 01.04.2005
Elsevier Science
Subjects
Applied sciences
Asymmetric graded lightly doped drain
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Graded lightly doped drain
Integrated circuits
Lightly doped drain
Microelectronic fabrication (materials and surfaces technology)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
Vertical channel nMOSFET
Vertical channel nMOSFET
Lightly doped drain
Asymmetric graded lightly doped drain
Graded lightly doped drain
MOSFET
Ion implantation
Short channel
Microelectronic fabrication
Direct current
Complementary MOS technology
Impurity diffusion
Vertical channel
NMOS technology
Electrical characteristic
Planar technology
Online AccessGet full text

Cover

More Information
Summary:A novel vertical channel nMOSFET with an asymmetric graded lightly doped drain (AGLDD) is first proposed and experimentally demonstrated. The vertical AGLDD structure is achieved by conventional ion implantation and impurity diffusion. The device fabrication is compatible with planar CMOS technology. The novel transistor shows very good immunity of short channel effects in DC characteristics.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2004.12.069