Wafer sojourn time fluctuation analysis for time-constrained dual-arm multi-cluster tools with activity time variation
In semiconductor manufacturing systems, a time-constrained multi-cluster tool should be scheduled such that a wafer stays in a process chamber in a given time range to satisfy a wafer residency time constraint. In practice, activity time is subject to variation. It could lead to some fluctuation of...
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Published in | International journal of computer integrated manufacturing Vol. 34; no. 7-8; pp. 734 - 751 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
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Taylor & Francis
03.08.2021
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Abstract | In semiconductor manufacturing systems, a time-constrained multi-cluster tool should be scheduled such that a wafer stays in a process chamber in a given time range to satisfy a wafer residency time constraint. In practice, activity time is subject to variation. It could lead to some fluctuation of wafer residency time in a process chamber. Hence, it is crucial to analyze how wafer residency time varies with activity time variation. This issue is especially challenging for multi-cluster tools. This work focuses on determining the exact upper bound of wafer sojourn time delay resulted from activity time variation for dual-arm multi-cluster tools. After discussing their dynamic behaviours, it presents a two-level real-time operational architecture and a real-time control policy. Based on them, this work derives for the first time an efficient algorithm to calculate the exact upper bound of wafer sojourn time delay in a process chamber. As a result, engineers can test whether a given schedule is feasible. Several examples of industrial significance are used to demonstrate the application of the proposed approach. |
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AbstractList | In semiconductor manufacturing systems, a time-constrained multi-cluster tool should be scheduled such that a wafer stays in a process chamber in a given time range to satisfy a wafer residency time constraint. In practice, activity time is subject to variation. It could lead to some fluctuation of wafer residency time in a process chamber. Hence, it is crucial to analyze how wafer residency time varies with activity time variation. This issue is especially challenging for multi-cluster tools. This work focuses on determining the exact upper bound of wafer sojourn time delay resulted from activity time variation for dual-arm multi-cluster tools. After discussing their dynamic behaviours, it presents a two-level real-time operational architecture and a real-time control policy. Based on them, this work derives for the first time an efficient algorithm to calculate the exact upper bound of wafer sojourn time delay in a process chamber. As a result, engineers can test whether a given schedule is feasible. Several examples of industrial significance are used to demonstrate the application of the proposed approach. |
Author | Qiao, Yan Su, Rong Wu, Naiqi Zhang, Chunjiang Yang, Fajun |
Author_xml | – sequence: 1 givenname: Fajun surname: Yang fullname: Yang, Fajun organization: Nanyang Technological University – sequence: 2 givenname: Naiqi surname: Wu fullname: Wu, Naiqi email: nqwu@must.edu.mo organization: Macau University of Science and Technology – sequence: 3 givenname: Yan surname: Qiao fullname: Qiao, Yan organization: Macau University of Science and Technology – sequence: 4 givenname: Rong surname: Su fullname: Su, Rong organization: Nanyang Technological University – sequence: 5 givenname: Chunjiang surname: Zhang fullname: Zhang, Chunjiang organization: Huazhong University of Science and Technology |
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SubjectTerms | multi-cluster tools real-time scheduling Semiconductor manufacturing systems wafer residency time constraint |
Title | Wafer sojourn time fluctuation analysis for time-constrained dual-arm multi-cluster tools with activity time variation |
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