Surface integrity and wafer-thickness variation analysis of ultra-thin silicon wafers sliced using wire-EDM

• Published in: Advances in materials and processing technologies (Abingdon, England) Vol. 5; no. 3; pp. 512 - 525
• Main Authors: Joshi, Kamlesh, Bhandarkar, Upendra V., Joshi, Suhas S.
• Format: Journal Article
• Language: English
• Published: Taylor & Francis 03.07.2019
• Subjects: kerf-loss; photo-voltaic; Si ingot; surface roughness; Ultra-thin wafers; wire-EDM
• ISSN: 2374-068X; 2374-0698
• DOI: 10.1080/2374068X.2019.1636185

The defect-free ultra-thin Si wafers with high surface quality have a huge demand in the solar cell-based industry. However, the currently employed wafer slicing methods result in various defects like wafer warpage, variation in thickness, surface and sub-surface cracks, and twin boundaries along with high surface roughness of around 3-5 µm. Therefore, in order to minimise the effect of mechanical machining on the wafer produced, wire-EDM as an alternative method has received attention in the recent past. This work presents the experimentation to understand the effect of wire-EDM on the surface quality and the wafer-thickness variation along the wafer height. The results show that the variation in wafer thickness can be minimised by increasing the parametric values of wire tension, wire feed, and dielectric flushing pressure. These parametric conditions help in better removal of clogged debris in the inter-electrode gap, which in turn improves the slicing process efficiency. The surface roughness values were found to be present in the range of 1 to 2.3 µm. In general, craters due to plasma sparks were visible on the wafer surface while analyzing through SEM micrographs, which also contributes to the surface roughness.