An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

• Published in: Journal of semiconductor technology and science Vol. 13; no. 4; pp. 367 - 380
• Main Authors: Bhushan, Shiv, Sarangi, Santunu, Gopi, Krishna Saramekala, Santra, Abirmoya, Dubey, Sarvesh, Tiwari, Pramod Kumar
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.08.2013
• Subjects: 전기공학; x< Ge< Double-material-gate(DMG); drain induced barrier lowering(DIBL); 1-x< hot carrier effect(HCE); SUB> strained-silicon(s-Si) on silicon-germanium (Si< MOSFETs
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2013.13.4.367

In this paper, an analytical thresholdvoltage model is developed for a short-channeldouble-material-gate (DMG) strained-silicon ( s −Si )on silicon-germanium ( 1 X X Si − Ge ) MOSFET structure. The proposed threshold voltage model is based on theso called virtual-cathode potential formulation. Thevirtual-cathode potential is taken as minimumchannel potential along the transverse direction of thechannel and is derived from two-dimensional (2D)potential distribution of channel region. The 2Dchannel potential is formulated by solving the 2DPoisson’s equation with suitable boundary conditionsin both the strained-Si layer and relaxed 1 X X Si − Gelayer. The effects of a number of device parameterslike the Ge mole fraction, Si film thickness and gatelengthratio have been considered on thresholdvoltage. Further, the drain induced barrier lowering(DIBL) has also been analyzed for gate-length ratioand amount of strain variations. The validity of thepresent 2D analytical model is verified with ATLASTM,a 2D device simulator from Silvaco Inc. KCI Citation Count: 1