Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications
Caches use data very differently than main memory does, so DRAM caches can have dramatically different refresh requirements. Making canonical assumptions about retention times in DRAM can be drastic overkill within the cache context. Using standard refresh rates may be unnecessary, and can be a sign...
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Published in | IEEE MICRO Vol. 28; no. 6; pp. 47 - 56 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
Los Alamitos
IEEE
01.11.2008
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | Caches use data very differently than main memory does, so DRAM caches can have dramatically different refresh requirements. Making canonical assumptions about retention times in DRAM can be drastic overkill within the cache context. Using standard refresh rates may be unnecessary, and can be a significant waste of cache utilization and power. In this article, we view "retention time" in a new way by using statistical populations more appropriate for caches, and we suggest uses of a cache's inherent error- control mechanisms to reduce refresh rates by several orders of magnitude. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0272-1732 1937-4143 |
DOI: | 10.1109/MM.2008.93 |