Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications

Caches use data very differently than main memory does, so DRAM caches can have dramatically different refresh requirements. Making canonical assumptions about retention times in DRAM can be drastic overkill within the cache context. Using standard refresh rates may be unnecessary, and can be a sign...

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Bibliographic Details
Published inIEEE MICRO Vol. 28; no. 6; pp. 47 - 56
Main Authors Emma, P.G., Reohr, W.R., Meterelliyoz, M.
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.11.2008
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Availability
Cache
Capacitors
Circuits
CMOS process
DRAM
DRAM chips
Dynamic random access memory
Logic devices
Populations
Random access memory
Read-write memory
Subthreshold current
Threshold voltage
Transistors
Utilization
Wastes
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Summary:Caches use data very differently than main memory does, so DRAM caches can have dramatically different refresh requirements. Making canonical assumptions about retention times in DRAM can be drastic overkill within the cache context. Using standard refresh rates may be unnecessary, and can be a significant waste of cache utilization and power. In this article, we view "retention time" in a new way by using statistical populations more appropriate for caches, and we suggest uses of a cache's inherent error- control mechanisms to reduce refresh rates by several orders of magnitude.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2008.93