An algorithm to enumerate all rectangular dual graphs

Due to the recent development of VLSI technology, circuits have begun to be made on LSI chips in every field of industry. In the layout design, one of the LSI design processes, the main objective, is to minimize the chip area to increase the efficiency and yield rate of ICs. Thus, it is important to...

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Published inElectronics & communications in Japan. Part 3, Fundamental electronic science Vol. 72; no. 3; pp. 34 - 46
Main Authors Tani, Katsunori, Shirakawa, Isao, Tsukiyama, Shuji
Format Journal Article
LanguageEnglish
Published New York Wiley Subscription Services, Inc., A Wiley Company 1989
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Summary:Due to the recent development of VLSI technology, circuits have begun to be made on LSI chips in every field of industry. In the layout design, one of the LSI design processes, the main objective, is to minimize the chip area to increase the efficiency and yield rate of ICs. Thus, it is important to find a good floor plan in the sense of area efficiency. This paper considers the problem of enumerating all rectangular dual graphs which are useful in floor plan design of VLSI using the notion of rectangular dual graph. We present an efficient algorithm which runs in O(|V|2) per one rectangular dual graph to be enumerated for a given maximal planar graph G0, where V is a vertex set of G0.
Bibliography:istex:CC7B2D9B20D448F779CC6FAC3505BCBE2E7D0BAC
ark:/67375/WNG-28W3GDL8-T
ArticleID:ECJC4430720304
Isao Shirakawa graduated in 1963 from Dept. of Electronics Engineering, Faculty of Engineering, Osaka University, where he obtained his M.S. in 1965 and Ph.D. in 1968. In 1968 he was a Research Associate at Osaka University, and in 1973 became an Associate Professor and Professor in 1987 in the Dept. of Electronics Engineering. During 1974‐1975 he was a Visiting Researcher at the University of California, Berkeley, USA. He is engaged mainly in the research on VLSI‐CAD methodologies, especially on parallel processing. He is the co‐author of Graphs and Networks and Exercises in Graph Theory, Corona Publishing Co.
Katsunori Tani graduated in 1986 from Dept. of Electronics Engineering, Faculty of Engineering, Osaka University, where he is currently in the Master's program. He is engaged in research concerning automation of VLSI placement design. He is a member of IEEE.
Shuji Tsukiyama graduated in 1972 from Dept. of Electronics Engineering, Faculty of Engineering, Osaka University. He then joined Osaka University as a Research Associate. In 1987 he became an Associate Professor. Since April 1987 he has been an Associate Professor on the Faculty of Science and Engineering, Dept. of Electrical Engineering, Chuo University. He has been engaged in research on computer‐aided circuit design and graph theory. He obtained a Dr. of Engineering degree from there in 1977. He is a member of IEEE; and the Information Processing Society of Japan.
ISSN:1042-0967
1520-6440
DOI:10.1002/ecjc.4430720304