Energy efficiency enhancements for semiconductors, communications, sensors and software achieved in cool silicon cluster project

• Published in: European physical journal. Applied physics Vol. 63; no. 1; p. 14402
• Main Authors: Ellinger, Frank, Mikolajick, Thomas, Fettweis, Gerhard, Hentschel, Dieter, Kolodinski, Sabine, Warnecke, Helmut, Reppe, Thomas, Tzschoppe, Christoph, Dohl, Jan, Carta, Corrado, Fritsche, David, Tretter, Gregor, Wiatr, Maciej, Kronholz, Stefan Detlef, Mikalo, Ricardo Pablo, Heinrich, Harald, Paulo, Robert, Wolf, Robert, Hübner, Johannes, Waltsgott, Johannes, Meißner, Klaus, Richter, Robert, Michler, Oliver, Bausinger, Markus, Mehlich, Heiko, Hahmann, Martin, Möller, Henning, Wiemer, Maik, Holland, Hans-Jürgen, Gärtner, Roberto, Schubert, Stefan, Richter, Alexander, Strobel, Axel, Fehske, Albrecht, Cech, Sebastian, Aßmann, Uwe, Pawlak, Andreas, Schröter, Michael, Finger, Wolfgang, Schumann, Stefan, Höppner, Sebastian, Walter, Dennis, Eisenreich, Holger, Schüffny, René
• Format: Journal Article
• Language: English
• Published: Les Ulis EDP Sciences 01.07.2013
• ISSN: 1286-0042; 1286-0050
• DOI: 10.1051/epjap/2013120480

An overview about the German cluster project Cool Silicon aiming at increasing the energy efficiency for semiconductors, communications, sensors and software is presented. Examples for achievements are: 1000 times reduced gate leakage in transistors using high-fc (HKMG) materials compared to conventional poly-gate (SiON) devices at the same technology node; 700 V transistors integrated in standard 0.35 μm CMOS; solar cell efficiencies above 19% at < 200 W/m2 irradiation; 0.99 power factor, 87% efficiency and 0.088 distortion factor for dc supplies; 1 ns synchronization resolution via Ethernet; database accelerators allowing 85% energy savings for servers; adaptive software yielding energy reduction of 73% for e-Commerce applications; processors and corresponding data links with 40% and 70% energy savings, respectively, by adaption of clock frequency and supply voltage in less than 20 ns; clock generator chip with tunable frequency from 83-666 MHz and 0.62-1.6 mW dc power; 90 Gb/s on-chip link over 6 mm and efficiency of 174 fJ/mm; dynamic biasing system doubling efficiency in power amplifiers; 60 GHz BiCMOS frontends with dc power to bandwidth ratio of 0.17 mW/MHz; driver assistance systems reducing energy consumption by 10% in cars