Testing the blade resilient asynchronous template

As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worst-case conditions. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins. These arch...

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Bibliographic Details
Published inAnalog integrated circuits and signal processing Vol. 106; no. 1; pp. 219 - 234
Main Authors Kuentzer, Felipe A., Juracy, Leonardo R., Moreira, Matheus T., Amory, Alexandre M.
Format Journal Article
LanguageEnglish
Published New York Springer US 2021
Springer Nature B.V
Subjects
Circuits and Systems
Electrical Engineering
Energy consumption
Energy efficiency
Engineering
Integrated circuits
Signal,Image and Speech Processing
Silicon
Testability
Design for Testability
Delay faults
Asynchronous design
Blade
Stuck-at faults
Timing resilient design
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Summary:As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worst-case conditions. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins. These architectures allow improving system performance and reducing energy consumption. Asynchronous systems, on the other hand, have the potential to improve energy efficiency and performance. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. This paper demonstrates that scan chains can be prohibitive for Blade due to their high silicon costs., which can reach more than 100%. Then, it proposes an alternative test approach that allows concurrent testing, stuck-at, and delay testing. The test approach is based on the reuse the Blade features to provide testability, with silicon area overheads between 4 and 7%.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-020-01651-8