An Optimization Technique for Low-Energy Embedded Memory Systems

• Published in: IPSJ Transactions on System LSI Design Methodology Vol. 2; pp. 239 - 249
• Main Authors: Matsumura, Tadayuki, Ishihara, Tohru, Yasuura, Hiroto
• Format: Journal Article
• Language: English
• Published: Information Processing Society of Japan 2009
• Subjects: Architecture; Delay; Dynamical systems; Dynamics; Energy consumption; Energy use; Noise; Optimization
• ISSN: 1882-6687; 1882-6687
• DOI: 10.2197/ipsjtsldm.2.239

On-chip memories generally use higher supply (VDD) and higher threshold (Vth) voltages than those of logic parts to improve the static noise margin and to suppress the static energy consumption. However, the higher VDD increases the dynamic energy consumption. This paper proposes a hybrid memory architecture which consists of the following two regions; (1) a dynamic energy conscious region which uses low VDD and Vth and (2) a static energy conscious region which uses high VDD and Vth. The proposed architecture is applied to a scratchpad memory. This paper also proposes an optimization problem for finding the optimal code allocation and the memory configuration simultaneously, which minimizes the total energy consumption of the memory under constraints of a static noise margin (SNM), a write margin (WM) and a memory access delay. The memory configuration is defined by a memory division ratio, a β ratio and a VDD. Experimental results demonstrate that the total energy consumption of our original 90nm SRAM can be reduced by 62.9% at the best case with a 4.56% area overhead without degradations of SNM, WM and access delay.