A Fully Integrated 0.13-μm CMOS 40-Gb/s Serial Link Transceiver

• Published in: IEEE journal of solid-state circuits Vol. 44; no. 5; pp. 1510 - 1521
• Main Authors: KIM, Jeong-Kyoum, KIM, Jaeha, GYUDONG KIM, JEONG, Deog-Kyoon
• Format: Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 01.05.2009
• Subjects: Applied sciences; Circuit boards; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clocks; CMOS; Connectors; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Equalizers; Exact sciences and technology; Integrated circuits; Jitter; Logic; Oscillators, resonators, synthetizers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transceivers; Phase measurement; Prototype; Feedback regulation; Equalizer; Clock; BGA technology; Transceiver; equalizer, sampler; CDR; Integrated circuit bonding; CMOS; PLL; Energy dissipation; Data recovery; Complementary MOS technology; Electronic packaging; phase detector; Charge pumping; transmitter; Timing jitter; Serial transmission; Current-mode logic; Voltage controlled oscillator; high speed; Receiver; Microstrip resonator; inductive peaking; Clock recovery; quadrature VCO; Latch circuit; Soldered joint; Sampler; Serial link; Printed circuit
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2017973

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-mum CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low f sub(T)of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4 times 2.9 mm super(2) with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2 super(15) -1 PRBS data is 1.85 ps sub(rms) over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ps sub(rms) and the measured BER of the transceiver is less than 10 super(-) super(14) .