Parallel computer vision on a reconfigurable multiprocessor network

• Published in: IEEE transactions on parallel and distributed systems Vol. 8; no. 3; pp. 292 - 309
• Main Authors: Ehandarkar, S.M., Arabnia, H.R.
• Format: Journal Article
• Language: English
• Published: IEEE 01.03.1997
• Subjects: Computer architecture; Computer vision; Hardware; Hypercubes; Image edge detection; Network topology; Performance loss; Reconfigurable architectures; Switches; Timing
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/71.584095

A novel reconfigurable architecture based on a multiring multiprocessor network is described. The reconfigurability of the architecture is shown to result in a low network diameter and also a low degree of connectivity for each node in the network. The mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. The architecture is shown to contain 2D mesh topologies of varying sizes and also a single one factor of the Boolean hypercube in any given configuration. A large class of algorithms for the 2D mesh and the Boolean n-cube are shown to map efficiently on the proposed architecture without loss of performance. The architecture is shown to be well suited for a number of problems in low and intermediate level computer vision such as the FFT, edge detection, template matching, and the Hough transform. Timing results for typical low and intermediate level vision algorithms on a transputer based prototype are presented.