Design of ATM AAL1 SAR for circuit emulation

The asynchronous transfer mode (ATM) adaptation layer type 1 (AAL1) segmentation and reassembly (SAR) are designed and implemented by the field programmable gate array (FPGA). The SAR header is generated and processed in the FPGA and the SAR payload is stored in an external first-in-first-out (FIFO)...

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Bibliographic Details
Published inIEEE transactions on communications Vol. 46; no. 9; pp. 1117 - 1121
Main Authors Lee, Yih-Chang, Kao, Tain-Lieng, Wu, Kou-Tan
Format Journal Article
LanguageEnglish
Published IEEE 01.09.1998
Subjects
Asynchronous transfer mode
Circuit testing
Clocks
Emulation
Field programmable gate arrays
Frequency
Jitter
Printed circuits
Protocols
Prototypes
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Summary:The asynchronous transfer mode (ATM) adaptation layer type 1 (AAL1) segmentation and reassembly (SAR) are designed and implemented by the field programmable gate array (FPGA). The SAR header is generated and processed in the FPGA and the SAR payload is stored in an external first-in-first-out (FIFO) device. A method to recover the source clock, called synchronous residual time stamp (SRTS), is implemented. The designed AAL1 SAR FPGA is properly tested in a prototype circuit board.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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ISSN:0090-6778
1558-0857
DOI:10.1109/26.718553