Profiling interface traps in MOS transistors by the DC current-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peake...

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Bibliographic Details
Published inIEEE electron device letters Vol. 17; no. 2; pp. 72 - 74
Main Authors Chih-Tang Sah, Neugroschel, A., Han, K.M., Kavalieros, J.T.
Format Journal Article
LanguageEnglish
Published IEEE 01.02.1996
Subjects
Charge carrier processes
Charge pumps
Current measurement
Density measurement
Electron traps
Leakage current
MOSFETs
Spontaneous emission
Stress measurement
Voltage
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Summary:Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10/sup 11/ traps/cm 2 generated by channel hot electron stress.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0741-3106
1558-0563
DOI:10.1109/55.484127