On wirelength estimations for row-based placement

Wirelength estimation in very large scale integration layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during top-down floorplanning and placement of cell-bas...

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Bibliographic Details
Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 18; no. 9; pp. 1265 - 1278
Main Authors Caldwell, A.E., Kahng, A.B., Mantik, S., Markov, I.L., Zelikovsky, A.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.09.1999
Institute of Electrical and Electronics Engineers
Subjects
Annealing
Applied sciences
Assessments
Blocking
Circuit optimization
Complexity
Computer science
Correlation
Costs
Design engineering
Design methodology
Design. Technologies. Operation analysis. Testing
Electronics
Estimates
Exact sciences and technology
Integrated circuits
Placement
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Steiner trees
Timing
Very large scale integration
Wiring
VLSI circuit
Interconnection
Length
Estimation
Computer aided design
Integrated circuit
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Summary:Wirelength estimation in very large scale integration layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during top-down floorplanning and placement of cell-based designs. Our methods give accurate, linear-time approaches, typically with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). Our techniques offer advantages not only for early on-line wirelength estimation during top-down placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several contributions, including (1) insight into the contrast between region-based and bounding box-based rectilinear Steiner minimal tree (RStMT) estimation techniques; (2) empirical assessment of the correlations between pin placements of a multipin net that is contained in a block; and (3) new wirelength estimates that are functions of a block's complexity (number of cell instances) and aspect ratio.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:0278-0070
1937-4151
DOI:10.1109/43.784119