The effects of annealing on the switching characteristics of an ion-implanted silicon MESFET

• Published in: IEEE transactions on electron devices Vol. 36; no. 5; pp. 920 - 929
• Main Authors: Chattopadhyay, S.N., Pal, B.B.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.05.1989; Institute of Electrical and Electronics Engineers
• Subjects: Annealing; Applied sciences; Capacitance; Electronics; Exact sciences and technology; Implants; Impurities; Lattices; MESFETs; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Shape; Silicon; Temperature; Threshold voltage; Transistors; Annealing; Heat treatment; Silicon; Metal semiconductor field effect transistor; Switching; Integrated circuit
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.299674

The gate-source and gate-drain capacitances and the drain-source resistance are calculated in the region below pinchoff in the postimplanted annealed condition. It is observed that the capacitances decrease and the resistance increases compared to the case where diffusion of impurity ions due to annealing is not considered. P, B, As, Sb, Ga, and Al dopants are used for the calculation. The delay time is found to be mostly unaffected by annealing. The capacitances in the region above pinchoff show an increase as a result of annealing in the enhancement device compared to the case when diffusion is not taken into account. These capacitances are mainly due to the sidewalls of the space-charge region and are dependent on the threshold voltage, which decreases at higher anneal temperatures in the enhancement mode.< >