Optimization of the drain-side configuration in ESD-protection SCR-LDMOS for high holding-voltage applications

A conventional silicon-controlled rectifier integrated into a laterally diffused MOSFET (SCR-LDMOS) is studied through 2D TCAD simulations in order to obtain the maximum holding voltage without increasing the area consumption or degrading the power-to-failure robustness. A reference device with 150V...

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Bibliographic Details
Published inMicroelectronics and reliability Vol. 168; p. 115664
Main Authors Zunarelli, L., Rotorato, S., Gnani, E., Reggiani, S., Sankaralingam, R., Dissegna, M., Boselli, G.
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.05.2025
Subjects
Electrostatic discharge
Holding voltage
SCR-LDMOS
TCAD simulations
Thermal failure
TLP I-V
TLP I-V
SCR-LDMOS
TCAD simulations
Thermal failure
Holding voltage
Electrostatic discharge
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Summary:A conventional silicon-controlled rectifier integrated into a laterally diffused MOSFET (SCR-LDMOS) is studied through 2D TCAD simulations in order to obtain the maximum holding voltage without increasing the area consumption or degrading the power-to-failure robustness. A reference device with 150V trigger voltage, 3V holding voltage and an approximate thermal breakdown at 30 mA/μm is adopted. Different configurations of the drain-side region are compared, with the best solution showing a 5x improvement on the holding condition without a significant variation on the other figures of merit. •Tunable holding voltage is a key element for future self-protecting ESD cells.•2D TCAD simulations are used to address the role of the NBL isolation on the holding regime and thermal runaway.•SCR-LDMOS for high holding voltage are investigated providing the relevant physical understanding.•A preliminary analysis of the very-fast TLP characteristic and of the dynamic voltage overshoot under very fast rising time are presented.
ISSN:0026-2714
DOI:10.1016/j.microrel.2025.115664