Synchronization of pipelines

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 12; no. 8; pp. 1132 - 1146
• Main Authors: Sakallah, K.A., Mudge, T.N., Burks, T.M., Davidson, E.S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.1993; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuits; Clocks; Concurrent computing; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Latches; Pipeline processing; Processor scheduling; Propagation delay; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Space vector pulse width modulation; Synchronization; Timing; Experimental result; Pipeline processor; Phase synchronization; Integrated circuit; Clock; Modeling; Computer aided design; Cycle; Optimization
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.238606

A recently formulated general timing model of synchronous operation is applied to the special case of latch-controlled pipelined circuits. The model accounts for multiphase synchronous clocking, correctly captures the behavior of label-sensitive latches, handles both short- and long-path delays, accommodates wave pipelining, and leads to a comprehensive set of timing constraints. Concurrency of pipeline circuits is defined as a function of the clock schedule and degree of wave pipelining. The authors then identify a special class of clock schedules, coincident multiphase clocks, which provide a lower bound on the value of the optimum cycle time. It is shown that the region of feasible solutions for single-phase clocking can be nonconvex or even disjoint, and a closed-form expression for the minimum cycle time of a restricted but practical form of single-phase clocking is derived. The authors compare these forms of clocking on three pipeline examples and highlight some of the issues in pipeline synchronization.< >