FAMOS: an efficient scheduling algorithm for high-level synthesis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 12; no. 10; pp. 1437 - 1448
• Main Authors: Park, I.-C., Kyung, C.-M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.1993; Institute of Electrical and Electronics Engineers
• Subjects: Algorithm design and analysis; Applied sciences; Cost function; Design. Technologies. Operation analysis. Testing; Digital systems; Electronics; Exact sciences and technology; Hardware; High level synthesis; Integrated circuits; Iterative algorithms; Polynomials; Scheduling algorithm; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Time factors; Experimental result; Integrated circuit; Digital circuit; System synthesis; Scheduling; Algorithm; Selection function; Computer aided design; Implementation; Pipeline
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.256918

FAMOS, an iterative improvement scheduling algorithm for the high-level synthesis of digital systems, is described. The algorithm is based on a move acceptance strategy and various selection functions defined to represent the cost of hardware resources such as functional units and registers. A main feature of the algorithm is that it can escape from local minima. The algorithm can deal with diverse design styles such as multi-cycle operations, chained operations, pipelined datapaths, pipelined functional units and conditional branches. Register costs and maximal time constraints are also considered. To efficiently represent information on the design styles, a graph model called weighted precedence graph is proposed as a general model on which the scheduling algorithm is based. Despite the iterative nature, the proposed algorithm has a polynomial time complexity. Although the optimality of the algorithm is not guaranteed, optimal solutions were obtained for several examples available from the literature.< >