Nonprime memory systems and error correction in address translation

• Published in: IEEE transactions on computers Vol. 46; no. 1; pp. 75 - 79
• Main Author: Katti, R.S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.1997; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Arithmetic; Bandwidth; Built-in self-test; Cathode ray tubes; Computer errors; Distributed computing; Electronics; Error correction; Exact sciences and technology; Fault detection; Fault tolerant systems; Hardware; Optical computers; Vector processors; Computers; Vector processor; Theoretical study; System design; Error detection; Computer storage; Error correction
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/12.559804

Using a prime number p of memory banks on a vector processor allows a conflict-free access for any slice of p consecutive elements of a vector stored with a stride not multiple of p. To reject the use of a prime number of memory banks, it is generally advanced that address computation for such a memory system would require systematic Euclidean division by the number p. The Chinese Remainder Theorem allows a simple mapping of data onto the memory banks for which address computation does not require any Euclidean division. However, this requires that the number of words in each memory module m and p be relatively prime. We propose a method based on the Chinese Remainder Theorem for moduli with common factors that does not have such a restriction. The proposed method does not require Euclidean division and also results in an efficient error detection/correction mechanism for address translation.