An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform

• Published in: Microprocessors and microsystems Vol. 47; pp. 404 - 418
• Main Authors: Asan Basiri M., Mohamed, Mahammad Sk, Noor
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.11.2016
• Subjects: Convolution; DSP processor; Wavelet transform; DSP processor; Convolution; Wavelet transform
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2016.08.007

•In this work, VLSI architectures with less delay/area for lifting based DWT are proposed.•The proposed logic used for area efficient DWT is to perform the whole operation with one processing element.•The proposed logic used for delay efficient DWT is to perform the whole operation with multiple processing elements in parallel.•In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. In this paper, high performance VLSI architectures for lifting based 1D and 2D-Discrete wavelet transforms (DWTs) are proposed. The proposed logic used for area efficient lifting based DWT is to perform the whole operation with one processing element. Similarly, the proposed logic used for delay efficient lifting based DWT is to perform the whole operation with multiple processing elements in parallel. In both the cases, the processing element consists of one floating point adder and one proposed fused multiply add design. The proposed and existing lifting based 1D and 2D lifting based DWTs are implemented with 45 nm technology. The results show that the proposed designs achieve significant improvement compared with existing architectures. For example, 9-point 2-parallel proposed (9, 7) single level 1D-DWT achieves 33.5% of reduction in total cycle delay compared with direct form. Similarly, 9-point single PE proposed (9, 7) single level 1D-DWT achieves 59.8% and 75.5% of reduction in total area and net power over direct form respectively.