Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process

• Published in: Journal of semiconductors Vol. 31; no. 8; pp. 70 - 73
• Main Author: 刘勇 唐昭焕 王志宽 杨永晖 杨卫东 胡永贵
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.08.2010
• Subjects: BiCMOS工艺; 击穿电压; 工艺设计; 应用; 数字模拟转换器; 线性误差; 耗尽型; 高电压
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/31/8/084006

A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC（digital-to-analog converter）.With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS（N-type lightly-dosed-drain in MOS） with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were obtained.Measurement results showed that the converter had a reference temperature coefficient of less than±25 ppm/℃,a differential coefficient error of less than±0.3 LSB,and a linear error of less than±0.5 LSB.The depletion-mode NJFET and its compatible process can also be widely used for high-voltage ADCs or DACs.