PIN-preamp module and CDR-DMUX constituting a receiver for short-haul links up to 3.5 Gb/s

A 3.5-Gb/s two-chip receiver consisting of a preamp and a gate-array-based clock and data recovery demultiplexer (CDR-DMUX) is fabricated in a 25-GHz Si bipolar process. The preamp is mounted within a 5-mm-diameter PIN-diode package. Measurements show >10 dB excess gain if the input referred offs...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 33; no. 12; pp. 2247 - 2251
Main Authors Hauenschild, J., Friedrich, D., Herrle, J., Krug, J.
Format Journal Article
LanguageEnglish
Published IEEE 01.12.1998
Subjects
Clocks
Computer architecture
Diodes
Gain measurement
Optical amplifiers
Optical feedback
Optical receivers
Optical sensors
Packaging
Plastics
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Summary:A 3.5-Gb/s two-chip receiver consisting of a preamp and a gate-array-based clock and data recovery demultiplexer (CDR-DMUX) is fabricated in a 25-GHz Si bipolar process. The preamp is mounted within a 5-mm-diameter PIN-diode package. Measurements show >10 dB excess gain if the input referred offset of the CDR is restricted to <1.5 mV. The gate array is utilized to <30% and mounted in a 100-pin plastic package. The CDR features an asynchronous-digital-hierarchy-compatible loss-of-signal detection tripping at a bit error rate >10/sup -3/. The chips dissipate 210 and 1500 mW from +5.0- and -4.5-V supplies, respectively.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:0018-9200
1558-173X
DOI:10.1109/4.735709