Packaging technology for the NEC SX-3 supercomputers

Since the performance of a computer system is mainly related to the machine cycle time, improvement of the logic circuit delay is the key for high-speed operations. In order to show how to reduce the logic circuit delay, the characteristics required for LSI chips and packaging technologies are discu...

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Bibliographic Details
Published inIEEE transactions on components, hybrids, and manufacturing technology Vol. 15; no. 4; pp. 411 - 417
Main Authors Murano, H., Watari, T.
Format Journal Article Conference Proceeding
LanguageEnglish
Published New York, NY IEEE 01.08.1992
Institute of Electrical and Electronics Engineers
Subjects
Applied sciences
Coaxial cables
Computers, microcomputers
Cooling
Delay effects
Electronics
Exact sciences and technology
Hardware
High performance computing
Integrated circuit interconnections
Large scale integration
Logic circuits
National electric code
Packaging machines
Supercomputers
Supercomputer
Delay time
VLSI circuit
Performance
Interconnection
Electronic packaging
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Summary:Since the performance of a computer system is mainly related to the machine cycle time, improvement of the logic circuit delay is the key for high-speed operations. In order to show how to reduce the logic circuit delay, the characteristics required for LSI chips and packaging technologies are discussed and the technological trends in packaging and their limitations are considered. As a typical application of high-performance packaging technology, the NEC SX-3 Supercomputer packaging is introduced, featuring 9 in/sup 2/ polyimide-ceramic substrates, a microchip carrier, flipped TAB carrier (FTC), high-density multichip packaging, high-speed coaxial cable interconnections, and a water cooling system.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0148-6411
1558-3082
DOI:10.1109/33.159867