Processor-based built-in self-test for embedded DRAM

• Published in: IEEE journal of solid-state circuits Vol. 33; no. 11; pp. 1731 - 1740
• Main Authors: Dreibelbis, J., Barth, J., Kalter, H., Kho, R.
• Format: Journal Article
• Language: English
• Published: IEEE 01.11.1998
• Subjects: AC generators; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit testing; Clocks; Engines; Logic programming; Logic testing; Random access memory
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.726568

A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256/spl times/16/spl times/128 to 2 K/spl times/16/spl times/256 (Word/spl times/Bit/spl times/Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations.