A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory

• Published in: IEEE journal of solid-state circuits Vol. 29; no. 11; pp. 1366 - 1373
• Main Authors: Tanaka, T., Tanaka, Y., Nakamura, H., Sakui, K., Oodaira, H., Shirota, R., Ohuchi, K., Masuoka, F., Hara, H.
• Format: Journal Article
• Language: English
• Published: IEEE 01.11.1994
• Subjects: Circuit noise; Costs; Coupling circuits; Flash memory; Handheld computers; Magnetic memory; Noise reduction; Power supplies; Threshold voltage; Voltage control
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.328638

This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure. A 3 V-only experimental NAND flash memory, developed in a 0.7-/spl mu/m NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-/spl mu/s random access time with a 2.7-V power supply. The page-programming is completed after the 40-/spl mu/s program and 2.8-/spl mu/s verify read cycle is iterated 4 times. The block-erasing time is 10 ms.< >