An 8-b 650-MHz folding ADC

An 8-b 650-MHz folding analog-to-digital converter (ADC) with analog error correction in the comparators is presented. With an input frequency of 150 MHz, 7.8 effective bits are obtained. The ADC is implemented in a 1- mu m 13-GHz triple-level interconnect bipolar process, requiring 850 mW from a si...

Full description

Saved in:
Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 27; no. 12; pp. 1662 - 1666
Main Authors van Valburg, J., van de Plassche, R.J.
Format Journal Article
LanguageEnglish
Published IEEE 01.12.1992
Subjects
Digital-analog conversion
Energy consumption
Error correction
Frequency conversion
Power amplifiers
Quantization
Sampling methods
Signal sampling
Voltage
Online AccessGet full text

Cover

More Information
Summary:An 8-b 650-MHz folding analog-to-digital converter (ADC) with analog error correction in the comparators is presented. With an input frequency of 150 MHz, 7.8 effective bits are obtained. The ADC is implemented in a 1- mu m 13-GHz triple-level interconnect bipolar process, requiring 850 mW from a single -4.5 V supply. The die size is 4.2 mm/sup 2/.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/4.173091