A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

• Published in: IEEE journal of solid-state circuits Vol. 32; no. 12; pp. 2048 - 2060
• Main Authors: Perrott, M.H., Tewksbury, T.L., Sodini, C.G.
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.1997
• Subjects: Bandwidth; Circuit optimization; CMOS process; Digital filters; Digital integrated circuits; Digital modulation; Frequency modulation; Frequency synthesizers; Prototypes; Transmitters
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.643663

A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-/spl mu/m CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH /spl Sigma/-/spl Delta/ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.