Ultra-Low Power Poly-Si TFTs with 10 nm Stacked Gate Oxide Fabricated by Nitric Acid Oxidation of Silicon (NAOS) Method

• Published in: ECS journal of solid state science and technology Vol. 4; no. 5; pp. N36 - N40
• Main Authors: Matsumoto, Taketoshi, Tsuji, Hiroshi, Terakawa, Sumio, Kobayashi, Hikaru
• Format: Journal Article
• Language: English
• Published: The Electrochemical Society 01.01.2015
• ISSN: 2162-8769; 2162-8777
• DOI: 10.1149/2.0151505jss

We have fabricated poly-silicon-based thin film transistors (TFTs) on glass substrates, and achieved ultra-low power consumption by driving at 1 V. The gate oxide layer has a 10 nm thick stacked structure with a 1.4 nm interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method and a 8.6 nm SiO2 layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method. The dynamic power consumption ratio of the NAOS-TFTs is 1/144 of that for the currently commercial TFTs with the driving voltage of 12 V and 80 nm gate oxide. The off-current decreases by ∼2 orders of magnitude by insertion of the ultra-thin NAOS SiO2 layer. The off-current decrease is attributed to i) blocking of the gate leakage current by the NAOS SiO2 layer, and ii) improvement of the quality of the deposited oxide on the NAOS SiO2 layer because of better nucleation, and consequently, the high on/off ration exceeding 109 is achieved.