Tertiarybutylarsine damage-free thin-film doping and conformal surface coverage of substrate-released horizontal Si nanowires

Conformal damage-free doping is the holy grail for 3D semiconductor device structures, such as those used in multi-gate and nanowire-based field effect transistors (FETs). The shape, dimension, pitch, and spacing of parallel conduction paths introduce increased complexity in a number of ways, but pa...

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Bibliographic Details
Published inApplied surface science Vol. 508; p. 145147
Main Authors Meaney, Fintan, Thomas, Kevin, MacHale, John, Mirabelli, Gioele, Kennedy, Noel, Connolly, James, Hatem, Chris, Petkov, Nikolay, Long, Brenda, Pelucchi, Emanuele, Duffy, Ray
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.04.2020
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Summary:Conformal damage-free doping is the holy grail for 3D semiconductor device structures, such as those used in multi-gate and nanowire-based field effect transistors (FETs). The shape, dimension, pitch, and spacing of parallel conduction paths introduce increased complexity in a number of ways, but particularly in the area of intentional impurity introduction for doping. To this end, gas-phase doping using tertiarybutylarsine (TBA) was employed to dope silicon-on-insulator (SOI) thin films basedcircular transfer length measurement (CTLM) devices with top silicon thicknesses down to 4.5 nm, and substrate-released horizontal Si nanowires. Dopant incorporation was observed with a peak active carrier concentration of ~7 × 1019 cm−3 after a 1050 °C rapid thermal anneal (RTA). An optimisation study showed that dopant incorporation is similar for varying exposure times to TBA gas, while increased exposure can cause roughening of the Si due to etching. Structural analysis by cross-sectional transmission electron microscopy (XTEM) and Energy-dispersive X-ray spectroscopy (EDX) showed conformal formation of an As-rich surface oxide on free standing nanowires, without surface etching or crystal damage, making this process promising for future gate-all-around (GAA) transistor architectures.
ISSN:0169-4332
1873-5584
DOI:10.1016/j.apsusc.2019.145147