A 16-bit cascaded sigma-delta pipeline A/D converter
A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static...
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| Published in | Journal of semiconductors Vol. 30; no. 5; pp. 103 - 108 |
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| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
IOP Publishing
01.05.2009
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1674-4926 |
| DOI | 10.1088/1674-4926/30/5/055010 |
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| Abstract | A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB. |
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| AbstractList | A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB. |
| Author | 李梁 李儒章 俞宙 张加斌 张俊安 |
| AuthorAffiliation | National Key Laboratory of Analog ICs, The 24th Institute, China Electronics Technology Group Corporation,Chongqing 400060, China |
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| Cites_doi | 10.1109/JSSC.2004.836230 10.1109/4.217978 10.1109/JSSC.2004.836232 10.1109/4.90025 10.1109/JSSC.1987.1052839 10.1109/4.75064 |
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| Notes | pipeline TN792 switched capacitor multi-bit sigma-delta ADC TN915.05 digital filter 11-5781/TN multi-bit sigma-delta ADC; oversampling; pipeline; digital filter; switched capacitor oversampling |
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| References | Nair K (5) 2004 11 1 12 2 3 4 Bosi A (9) 2005 Draxelmayr D (8) 2004 Limotyrakis S (7) 2004 Norsworthy S R (6) 1997 Razavi B (10) 2001 |
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| Snippet | A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed... |
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| SubjectTerms | CMOS工艺 Delta Sigma 模拟数字转换器 流水线模数转换器 管道 级联 过采样率 |
| Title | A 16-bit cascaded sigma-delta pipeline A/D converter |
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