A 16-bit cascaded sigma-delta pipeline A/D converter

• Published in: Journal of semiconductors Vol. 30; no. 5; pp. 103 - 108
• Main Author: 李梁 李儒章 俞宙 张加斌 张俊安
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.05.2009
• Subjects: CMOS工艺; Delta; Sigma; 模拟数字转换器; 流水线模数转换器; 管道; 级联; 过采样率
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/30/5/055010

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter （ADC） with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35μm CMOS process and achieves an SNR of 82 dB.