A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

• Published in: Journal of semiconductors Vol. 31; no. 6; pp. 39 - 43
• Main Author: 庄敏宏 张家伟 史德智 黄全洲 王志良 张胜良
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.06.2010
• Subjects: CMOS; ITS计划; TFT器件; 多晶硅薄膜晶体管; 工艺制造; 工艺简化; 掺杂分布; 轻掺杂漏
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/31/6/064003

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors（TFTs） has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer（LAITS）.By this LATITS scheme,a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus（or boron） dopant through the spacer,and then the n~＋-source/drain（n~＋-S/D）（or p~＋-S/D） region is formed via using the same photo-mask layer during CMOS integration.For both n-TFT and p-TFT devices,as compared to the sample with conventional single n~＋-S/D（or p~＋-S/D） structure,the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field.In addition,the resultant on-state currents only show slight degradation for the LATITS scheme.As a result,by the LATITS scheme,CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.