Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency

• Published in: Neurocomputing (Amsterdam) Vol. 474; pp. 128 - 140
• Main Authors: Yang, Liwei, Zhang, Huaipeng, Luo, Tao, Qu, Chuping, Aung, Myat Thu Linn, Cui, Yingnan, Zhou, Jun, Wong, Ming Ming, Pu, Junran, Do, Anh Tuan, Goh, Rick Siow Mong, Wong, Weng Fai
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 14.02.2022
• Subjects: Constraints-compatible mapping; Large-scale SNN; Neuromorphic computing; Resource-efficient compilation; Spiking neural networks; Large-scale SNN; Resource-efficient compilation; Constraints-compatible mapping; Neuromorphic computing; Spiking neural networks
• ISSN: 0925-2312; 1872-8286
• DOI: 10.1016/j.neucom.2021.12.021

•Configurable core combinations, called coresets, resolve fan-in/fan-out constraints.•Resource efficiency is greatly improved by coresets for neuromorphic computing.•Large-scale spiking neural network support is achieved by coresets.•Our end-to-end solution seamlessly supports TensorFlow, simulation, FPGA emulation. Crossbar-based neuromorphic chips promise improved energy efficiency for spiking neural networks (SNNs), but suffer from the limited fan-in/fan-out constraints and resource mapping inefficiency. In this paper, we propose a new hardware mechanism to enable configurable combination of cores, called coreset. Using this hierarchical method, our end-to-end CSM (which stands for the ‘CoreSet Method’) framework efficiently solves the fan-in/fan-out issues and significantly improves the resource efficiency. Experiment results show that CSM can efficiently support complex network structures as well as significantly improving accuracies. Up to 4.6% improvement compared with those achieved by other neuromorphic chips (i.e. IBM TrueNorth and Intel Loihi), on the CIFAR-10, CIFAR-100 and SVHN datasets is achieved, matching the accuracies of state-of-the-art SNN models. In addition, compared with IBM TrueNorth, CSM achieves improvements of up to 18.5×,6.04× and 3.33× in memory efficiency, core efficiency and extrapolated throughput, respectively, thus enabling support for large-scale modern networks (such as VGG). In fact, our method can find optimal core sizes for minimal silicon area. As a proof of concept, we have implemented an FPGA emulation of coreset-supported neuromorphic computing. It achieves up to 7,737× speed-up compared to software simulation, thus not only facilitating SNN structure exploration and verification in a timely manner, but also enabling earlier prototyping for better neuromorphic hardware performance investigation.