A statistical RCL interconnect delay model taking account of process variations

• Published in: Chinese physics B Vol. 20; no. 1; pp. 659 - 666
• Main Author: 朱樟明 万达经 杨银堂 恩云飞
• Format: Journal Article
• Language: English
• Published: IOP Publishing 2011
• Subjects: CMOS工艺; CMOS集成电路; Galerkin方法; 互连系统; 延迟模型; 纳米集成电路
• ISSN: 1674-1056; 2058-3834
• DOI: 10.1088/1674-1056/20/1/018401

As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.