A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography

• Published in: 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) pp. 637 - 644
• Main Authors: Jae-Seok Yang, Lu, K., Minsik Cho, Kun Yuan, Pan, D.Z.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2010
• Subjects: Benchmark testing; Capacitance; Circuits; Large-scale systems; Lithography; Minimization; Page description languages; Partitioning algorithms; Runtime; Timing
• ISBN: 9781424457656; 1424457653
• ISSN: 2153-6961; 2153-697X
• DOI: 10.1109/ASPDAC.2010.5419807

As double patterning lithography(DPL) becomes the leading candidate for sub-30 nm lithography process, we need a fast and lithography friendly decomposition framework. In this paper, we propose a multi-objective min-cut based decomposition framework for stitch minimization, balanced density, and overlay compensation, simultaneously. The key challenge of DPL is to accomplish high quality decomposition for large-scale layouts under reasonable runtime with the following objectives: a) the number of stitches is minimized, b) the balance between two decomposed layers is maximized for further enhanced patterning, c) the impact of overlay on coupling capacitance is reduced for less timing variation. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. An additional decomposition constraints for self-overlay compensation are obtained by integer linear programming(ILP). With the constraints, global decomposition is executed by our modified FM graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures.