Novel Design of Resource‐Constrained Quantum Reversible Logic Gates at Optimal Cost and Depth

• Published in: Journal of nanotechnology Vol. 2025; no. 1
• Main Authors: Prajapati, Mamtha, Killana, Kalyan Babu
• Format: Journal Article
• Language: English
• Published: New York John Wiley & Sons, Inc 2025; Wiley
• Subjects: Algorithms; Business metrics; Circuits; Commutation; Complexity; Constraints; Data processing; Design; Efficiency; Energy consumption; Error correction & detection; Fourier transforms; Gate counting; Gates (circuits); Large scale integration; Logic; Logic circuits; Logic design; Optimization; Quantum computing; Quantum phenomena; Relocation; Template matching; Very large scale integration
• ISSN: 1687-9503; 1687-9511
• DOI: 10.1155/jnt/9968645

Reversible logic computation and optimization of reversible circuits help synthesize applications characterized by ultra‐low power consumption, including quantum information processing, the field of nanotechnology, semiconductor technology, the field of optics, and very‐large‐scale integration (VLSI), among others. Reversible logic design is a growing research subject that evaluates and applies resources in new advancements. This article provides an optimized, unique, resource‐constrained universal quantum reversible gate for nanoscale applications that perform all fundamental logic operations. Optimization and gate relocation have enhanced a published and proposed design. Quantum reversible circuits are optimized for cost and depth via template matching, gate fusion (merging) and commutation, gate decomposition, and gate elimination. These methods reduce circuit complexity and size significantly. A step‐by‐step optimization of the quantum reversible logic design is first presented. The novel quantum reversible gates MRQ1, MRQ2, and M‐BUS are implemented and verified on the IBM Qiskit platform. The proposed reversible gates’ design complexity is assessed using 13 standard Boolean expressions. Proposed quantum reversible gates demonstrate an improvement in performance, covering a range of 12.5%–72.7% over prior designs in gate count, depth, and quantum cost. Gate count improved most, impacting other parameters and demonstrating the design’s resource efficiency.