A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation
A fast offset compensation method for high-gain amplifiers is presented that leverages a novel peak detector design and a dynamic, multi-tap feedback system to achieve roughly three orders of magnitude improvement in settling time over traditional compensation methods. Design tradeoffs between gain,...
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Published in | IEEE journal of solid-state circuits Vol. 41; no. 2; pp. 443 - 451 |
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Main Authors | , |
Format | Journal Article |
Language | English |
Published |
New York, NY
Institute of Electrical and Electronics Engineers
01.02.2006
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Subjects | |
Online Access | Get full text |
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Summary: | A fast offset compensation method for high-gain amplifiers is presented that leverages a novel peak detector design and a dynamic, multi-tap feedback system to achieve roughly three orders of magnitude improvement in settling time over traditional compensation methods. Design tradeoffs between gain, bandwidth, power dissipation, and noise performance of the limit amplifier are discussed. Measured results of a custom 3.125 Gb/s limit amplifier in 0.18 mu m CMOS employing the proposed compensation technique demonstrate a sub-1-ms settling time while still achieving less than 4 ps rms output jitter with a 2.5 mV peak-to-peak input at 2.5 Gb/s. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2005.862352 |