A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 2; pp. 443 - 451
• Main Authors: CRAIN, Ethan A, PERROTT, Michael H
• Format: Journal Article
• Language: English
• Published: New York, NY Institute of Electrical and Electronics Engineers 01.02.2006
• Subjects: Amplification; Amplifiers; Applied sciences; Circuit properties; Compensation; Design engineering; Design. Technologies. Operation analysis. Testing; Dynamical systems; Dynamics; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Gain; General equipment and techniques; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuits; Physics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing; Settling; Performance evaluation; Feedback system; offset; high speed; Power gain; Measurement sensor; Jitter; peak detector; Amplifier; Energy dissipation; Complementary MOS technology; Compensation; Root mean square value
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2005.862352

A fast offset compensation method for high-gain amplifiers is presented that leverages a novel peak detector design and a dynamic, multi-tap feedback system to achieve roughly three orders of magnitude improvement in settling time over traditional compensation methods. Design tradeoffs between gain, bandwidth, power dissipation, and noise performance of the limit amplifier are discussed. Measured results of a custom 3.125 Gb/s limit amplifier in 0.18 mu m CMOS employing the proposed compensation technique demonstrate a sub-1-ms settling time while still achieving less than 4 ps rms output jitter with a 2.5 mV peak-to-peak input at 2.5 Gb/s.