Learning in analog neural network hardware

• Published in: Computers & electrical engineering Vol. 19; no. 6; pp. 453 - 467
• Main Author: Tawel, Raoul
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.11.1993
• ISSN: 0045-7906; 1879-0755
• DOI: 10.1016/0045-7906(93)90021-I

Hardware implementations of neuroprocessor architectures are currently enjoying commercial availability for the first time ever. This development has been caused in part by the requirement for real-time solutions to time critical neural network applications. Massively parallel asynchronous neuromorphic representations are inherently capable of very high computational speeds when properly cast in the “right stuff”, i.e. electronic or optoelectronic hardware. However, hardware based learning in such systems is still at a primitive stage. In practise, simulations are typically performed in software, and the resulting synaptic weight capturing the input-output transformation subsequently quantized and down-loaded onto the neural hardware. However, because of the numerous discrepancies between the software and hardware, such systems are inherently poor in performance. In this paper we report on chip-in-the-loop learning systems assembled from custom analog “building blocks” hardware.