SPIDER: capacitance modelling for VLSI interconnections
An efficient method is presented to model the parasitic capacitance of VLSI interconnections. It is valid for conductors in a stratified medium which is considered to be a good approximation for the Si-SiO/sub 2/ system of which ICs are made. The model approximates the charge density on the conducto...
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Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 7; no. 12; pp. 1221 - 1228 |
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Main Authors | , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.12.1988
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
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Summary: | An efficient method is presented to model the parasitic capacitance of VLSI interconnections. It is valid for conductors in a stratified medium which is considered to be a good approximation for the Si-SiO/sub 2/ system of which ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a 'spider' of edges. The model has very low complexity as compared to previously presented models and achieves a high degree of precision within the range of validity of the stratified medium.< > |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0278-0070 1937-4151 |
DOI: | 10.1109/43.16800 |