Open/folded bit-line arrangement for ultra-high-density DRAM's

• Published in: IEEE journal of solid-state circuits Vol. 29; no. 4; pp. 539 - 542
• Main Authors: Takashima, D., Watanabe, S., Nakano, H., Oowaki, Y., Ohuchi, K.
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.1994
• Subjects: Circuit noise; Coupling circuits; Joining processes; Manufacturing; Multiplexing; Noise reduction; Phased arrays; Random access memory; Ultra large scale integration; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.280706

An open/folded bit-line (BL) arrangement for scaled DRAM's is proposed. This BL arrangement offers small die size and good array noise immunity. In this arrangement, one BL of an open BL pair is placed in between a folded BL pair, and the sense amplifiers (SA's) for open BL's and those for folded BL's are placed alternately between the memory arrays. This arrangement features a small 6F/sup 2/ memory cell, where F is the device feature size, and a relaxed SA pitch of 6F. The die size of a 64-Mb DRAM can be reduced to 81.6% compared with the one using the conventional folded BL arrangement. The BL-BL coupling noise is reduced to one-half of that of the conventional folded BL arrangement, thanks to the shield effect. Two new circuit techniques, 1) a multiplexer for connecting BL's to SA's, and 2) a binary-to-ternary code converter for the multiplexer have been developed to realize the new BL arrangement.< >