Charge collection in submicron CMOS/SOI technology

We present experimental measurements of charge collection spectroscopy from high energy ion strikes in submicron CMOS/SOI devices. Due to the specific structure of SOI technology, with symmetrical source and drain junctions, a direct equivalence between upset mechanism and charge collection is estab...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 44; no. 6; pp. 2124 - 2133
Main Authors Musseau, O., Ferlet-Cavrois, V., Campbell, A.B., Knudson, A.R., Stapor, W.J., McDonald, P.T., Pelloie, J.L., Raynaud, C.
Format Journal Article
LanguageEnglish
Published IEEE 01.12.1997
Subjects
Charge measurement
CMOS technology
Current measurement
Dielectric thin films
Isolation technology
MOSFETs
Single event upset
Spectroscopy
Testing
Thin film transistors
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Summary:We present experimental measurements of charge collection spectroscopy from high energy ion strikes in submicron CMOS/SOI devices. Due to the specific structure of SOI technology, with symmetrical source and drain junctions, a direct equivalence between upset mechanism and charge collection is established. The bipolar mechanism, responsible for the amplification of the deposited charge is discussed based on 2D device simulations. Based on the experimental data we determine qualitatively the influence of transistor geometry on the bipolar gain. Finally the limits of the usual SEU concepts (LET threshold and cross section) are discussed for scaled devices.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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content type line 23
ISSN:0018-9499
1558-1578
DOI:10.1109/23.659027