Parallel Quicksort using fetch-and-add

• Published in: IEEE transactions on computers Vol. 39; no. 1; pp. 133 - 138
• Main Authors: Heidelberger, P., Norton, A., Robinson, J.T.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.01.1990; Institute of Electrical and Electronics Engineers
• Subjects: Adaptive scheduling; Applied sciences; Computer science; control theory; systems; Dynamic scheduling; Exact sciences and technology; Heuristic algorithms; Load management; Parallel algorithms; Partitioning algorithms; Phase change random access memory; Processor scheduling; Scheduling algorithm; Software; Sorting; Utility programs; Multiprocessor; Parallel algorithm; Integrated planning; Sort routine; Computer system; Shared memory; Adaptive method; Sorting
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/12.46289

A parallelization of the Quicksort algorithm that is suitable for execution on a shared memory multiprocessor with an efficient implementation of the fetch-and-add operation is presented. The partitioning phase of Quicksort, which has been considered a serial bottleneck, is cooperatively executed in parallel by many processors through the use of fetch-and-add. The parallel algorithm maintains the in-place nature of Quicksort, thereby allowing internal sorting of large arrays. A class of fetch-and-add-based algorithms for dynamically scheduling processors to subproblems is presented. Adaptive scheduling algorithms in this class have low overhead and achieve effective processor load balancing. The basic algorithm is shown to execute in an average of O(log(N)) time on an N-processor PRAM (parallel random-access machine) assuming a constant-time fetch-and-add. Estimated speedups, based on simulations, are also presented for cases when the number of items to be sorted is much greater than the number of processors.< >