Critical evaluation of the performance of CMOS circuits incorporating double-implanted nMOS source and drain regions

• Published in: IEEE electron device letters Vol. 7; no. 4; pp. 211 - 213
• Main Authors: Bold, B.S., Brassington, M.P.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.04.1986; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Breakdown voltage; Circuit optimization; Degradation; Dielectric substrates; Electric resistance; Electricity supply industry; Electronics; Exact sciences and technology; Geometry; Implants; Integrated circuits; MOS devices; MOSFET circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Ion implantation; VLSI circuit; Arsenic; P n+ junction; Phosphorus; Field effect transistor; Operation study; High voltage; Disruptive voltage; Complementary MOS technology; Integrated circuit; Silicon; Delay time; Solid state oscillator
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/EDL.1986.26349

Graded n+ junctions, produced by implantation of arsenic and phosphorus, offer a simple but effective means of reducing electric fields in small geometry nMOSFET's, so suppressing hot-carrier phenomena. The performance of simple CMOS circuits employing graded n+ junctions is compared with that of circuits incorporating abrupt arsenic-only n+ regions. The detrimental effects of increased series resistance and Miller capacitances associated with the graded n+ regions are small and are compensated by the reduction in effective channel length which is also associated with graded junctions. This results in minimal net difference between the performance of circuits employing these two junction types. However, the advantages of graded n+ junctions with respect to the safe operation of small-geometry CMOS circuits at elevated supply voltages is clearly demonstrated.