A 40-nm 169mW Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices

• Published in: IEEE transactions on biomedical circuits and systems Vol. 19; no. 2; pp. 428 - 441
• Main Authors: Lo, Yi-Lin, Lo, Yu-Chen, Yang, Chia-Hsiang
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.04.2025; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: advanced imaging mode; algorithm-architecture co-optimization; Algorithms; Array signal processing; Beamforming; CMOS integrated circuits; Delays; Doppler effect; Elasticity Imaging Techniques - instrumentation; Elastography; Equipment Design; Gate counting; Hand-held ultrasound devices; Humans; Image Processing, Computer-Assisted; Imaging; Logic circuits; low-power design; Microprocessors; Plane waves; Power consumption; Power management; Pulse repetition frequency; Real time; Signal Processing, Computer-Assisted; Ultrasonic imaging; Ultrasonography - instrumentation; Ultrasound; Vectors
• ISSN: 1932-4545; 1940-9990; 1940-9990
• DOI: 10.1109/TBCAS.2024.3445968

Hand-held ultrasound devices have been widely used in the field of healthcare and power-efficient, real-time imaging is essential. This work presents the world's first ultrasound imaging processor supporting advanced modes, including vector flow imaging and elastography imaging. Plane-wave beamforming is utilized to ensure that the pulse repetition frequency (PRF) is sufficiently high for the advanced mode. The storage size and power consumption are minimized through algorithm-architecture co-optimization. The proposed plane-wave beamforming reduces the storage size of the required delay values by 43.7%. By exchanging the processing order, the storage size is reduced by 78.1% for elastography imaging. Parallel beamforming and interleaved firing are employed to achieve real-time imaging for all the supported modes. Fabricated in 40-nm CMOS technology, the proposed processor integrates 4.7M logic gates in core area of 3.24mm<inline-formula><tex-math notation="LaTeX">{}^{2}</tex-math></inline-formula>. This work achieves a 20.3<inline-formula><tex-math notation="LaTeX">\boldsymbol{\times}</tex-math></inline-formula> higher beamforming rate with 5.3-to-29.1<inline-formula><tex-math notation="LaTeX">\boldsymbol{\times}</tex-math></inline-formula> lower power consumption than the state-of-the-art design. It also has 60% lower hardware complexity (in terms of gate count), in addition to the capability for supporting the advanced mode.